Invention Application
US20150311172A1 Semiconductor Device and Method of Forming Bump-on-Lead Interconnection
审中-公开
半导体器件和形成凸点导联互连的方法
- Patent Title: Semiconductor Device and Method of Forming Bump-on-Lead Interconnection
- Patent Title (中): 半导体器件和形成凸点导联互连的方法
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Application No.: US14745056Application Date: 2015-06-19
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Publication No.: US20150311172A1Publication Date: 2015-10-29
- Inventor: Rajendra D. Pendse
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, LTD.
- Current Assignee: STATS ChipPAC, LTD.
- Current Assignee Address: SG Singapore
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/31

Abstract:
A semiconductor device has a semiconductor die with a plurality of composite bumps formed over a surface of the semiconductor die. The composite bumps have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. The composite bumps can also be tapered. Conductive traces are formed over a substrate with interconnect sites having edges parallel to the conductive trace from a plan view for increasing escape routing density. The interconnect site can have a width less than 1.2 times a width of the conductive trace. The composite bumps are wider than the interconnect sites. The fusible portion of the composite bumps is bonded to the interconnect sites so that the fusible portion covers a top surface and side surface of the interconnect sites. An encapsulant is deposited around the composite bumps between the semiconductor die and substrate.
Public/Granted literature
- US09385101B2 Semiconductor device and method of forming bump-on-lead interconnection Public/Granted day:2016-07-05
Information query
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