发明申请
- 专利标题： Methods of Fabrication and Testing of Three-Dimensional Stacked Integrated Circuit System-In-Package
- 专利标题（中）： 三维堆叠集成电路系统的封装形式和测试方法
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申请号： US14694868申请日： 2015-04-23
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公开(公告)号： US20150311188A1公开(公告)日： 2015-10-29
- 发明人: Jianhong MAO , Fengqin HAN , Zhiwei WANG , Wenfen CHANG
- 申请人： Shanghai Lexvu Opto Microelectronics Technology Co., Ltd.
- 优先权： CN201410168052.X 20140424
- 主分类号： H01L25/00
- IPC分类号： H01L25/00 ; H01L23/00 ; H01L21/66 ; H01L21/56
摘要：
The present invention provides a method of fabricating a 3D stacked IC SiP which includes: providing a first semiconductor wafer having a plurality of first dies formed thereon, each having a first wire bond pad and a first dielectric layer, at least a portion of the first wire bond pad is not covered by the first dielectric layer and constitutes an exposed area of the first die; providing a plurality of second dies, each having a second wire bond pad and a second dielectric layer, at least a portion of the second wire bond pad is not covered by the second dielectric layer and constitutes an exposed area of the second die different in size from that of the first die; aligning the second dies with the first dies and bonding the second dielectric layer to the first dielectric layer; plating the first semiconductor wafer bonded with the second dies.
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