Invention Application
- Patent Title: DIE WARPAGE CONTROL FOR THIN DIE ASSEMBLY
- Patent Title (中): 用于薄膜组件的DIE WARPAGE控制
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Application No.: US14796759Application Date: 2015-07-10
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Publication No.: US20150318258A1Publication Date: 2015-11-05
- Inventor: SANDEEP B. SANE , Shankar Ganapathysubramanian , Jorge Sanchez , Leonel R. Arana , Eric J. Li , Nitin A. Deshpande , Jiraporn Seangatith , Poh Chieh Benny Poon
- Applicant: INTEL CORPORATION
- Applicant Address: US CA SANTA CLARA
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA SANTA CLARA
- Main IPC: H01L23/00
- IPC: H01L23/00

Abstract:
Die warpage is controlled for the assembly of thin dies. In one example, a semiconductor die has a back side and a front side opposite the back side. The back side has a semiconductor substrate and the front side has components formed over the semiconductor substrate in front side layers. A backside layer is formed over the backside of the semiconductor die to resist warpage of the die when the die is heated and a plurality of contacts are formed on the front side of the die to attach to a substrate.
Public/Granted literature
- US09659899B2 Die warpage control for thin die assembly Public/Granted day:2017-05-23
Information query
IPC分类: