Invention Application
US20150333005A1 PLACEMENT OF MONOLITHIC INTER-TIER VIAS (MIVs) WITHIN MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) USING CLUSTERING TO INCREASE USABLE WHITESPAC 审中-公开
在单片三维(3D)集成电路(IC)(3DIC)中使用聚合增加可用的白色SPAC的单层互联VIAS(MIV)的放置

  • Patent Title: PLACEMENT OF MONOLITHIC INTER-TIER VIAS (MIVs) WITHIN MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) USING CLUSTERING TO INCREASE USABLE WHITESPAC
  • Patent Title (中): 在单片三维(3D)集成电路(IC)(3DIC)中使用聚合增加可用的白色SPAC的单层互联VIAS(MIV)的放置
  • Application No.: US14795914
    Application Date: 2015-07-10
  • Publication No.: US20150333005A1
    Publication Date: 2015-11-19
  • Inventor: Kambiz SamadiShreepad Amar PanthPratyush KamalYang Du
  • Applicant: QUALCOMM Incorporated
  • Main IPC: H01L23/522
  • IPC: H01L23/522 G06F17/50 H01L27/06
PLACEMENT OF MONOLITHIC INTER-TIER VIAS (MIVs) WITHIN MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) USING CLUSTERING TO INCREASE USABLE WHITESPAC
Abstract:
Placement of Monolithic Inter-tier Vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace is disclosed. In one embodiment, a method of placing MIVs in a monolithic 3DIC using clustering is provided. The method comprises determining if any MIV placement clusters are included within a plurality of initial MIV placements of a plurality of MIVs within an initial 3DIC layout plan. The method further comprises aligning each MIV of the plurality of MIVs within each MIV placement cluster in the initial 3DIC layout plan at a final MIV placement for each MIV placement cluster to provide a clustered 3DIC layout plan.
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