Invention Application
US20150340426A1 COMPONENT, FOR EXAMPLE NMOS TRANSISTOR, WITH AN ACTIVE REGION UNDER RELAXED COMPRESSIVE STRESS, AND ASSOCIATED DECOUPLING CAPACITOR
审中-公开
用于示例性NMOS晶体管的组件，具有在放大的压缩应力下的有源区域，以及相关的去耦电容器
- Patent Title: COMPONENT, FOR EXAMPLE NMOS TRANSISTOR, WITH AN ACTIVE REGION UNDER RELAXED COMPRESSIVE STRESS, AND ASSOCIATED DECOUPLING CAPACITOR
- Patent Title (中): 用于示例性NMOS晶体管的组件，具有在放大的压缩应力下的有源区域，以及相关的去耦电容器
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Application No.: US14715814Application Date: 2015-05-19
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Publication No.: US20150340426A1Publication Date: 2015-11-26
- Inventor: Sylvie Wuidart , Christian Rivero , Guilhem Bouton , Pascal Fornara
- Applicant: STMICROELECTRONICS (ROUSSET) SAS
- Applicant Address: FR Rousset
- Assignee: STMICROELECTRONICS (ROUSSET) SAS
- Current Assignee: STMICROELECTRONICS (ROUSSET) SAS
- Current Assignee Address: FR Rousset
- Priority: FR1454552 20140521
- Main IPC: H01L49/02
- IPC: H01L49/02 ; H01L27/06 ; H01L29/423 ; H01L27/115 ; H01L29/78
Abstract:
An integrated circuit includes a substrate and a circuit component (such as a MOS device or resistance) disposed at least partially within an active region of the substrate limited by an insulating region. A capacitive structure including a first electrode (for connection to a first potential such as ground) and a second electrode (for connection to a second potential such as a supply voltage) is provided in connection with the insulating region. One of the first and second electrodes is situated at least in part within the insulating region. The capacitive structure is thus configured in order to allow a reduction in compressive stresses within the active region.
Information query
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