Invention Application
- Patent Title: EXPLICIT BARRIER SCHEDULING MECHANISM FOR PIPELINING OF STREAM PROCESSING ALGORITHMS
- Patent Title (中): 用于流水线加工算法的显式障碍物调度机制
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Application No.: US14288541Application Date: 2014-05-28
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Publication No.: US20150347185A1Publication Date: 2015-12-03
- Inventor: James C. Holt , Joseph P. Gergen , David B. Kramer , William C. Moyer
- Applicant: James C. Holt , Joseph P. Gergen , David B. Kramer , William C. Moyer
- Applicant Address: US TX Austin
- Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee: FREESCALE SEMICONDUCTOR, INC.
- Current Assignee Address: US TX Austin
- Main IPC: G06F9/48
- IPC: G06F9/48 ; G06F9/38

Abstract:
A method for pipelined data stream processing of packets includes determining a task to be performed on each packet of a data stream, the task having a plurality of task portions including a first task portion. Determining the first task portion is to process a first packet. In response to determining a first storage location stores a first barrier indicator, enabling the first task portion to process the first packet and storing a second barrier indicator at the first location. Determining the first task portion is to process a second next-in-order packet. In response to determining the first location stores the second barrier indicator, preventing the first task portion from processing the second packet. In response to a first barrier clear indicator, storing the first barrier indicator at the first location, and in response, enabling the first task portion to process the second packet.
Public/Granted literature
- US09207979B1 Explicit barrier scheduling mechanism for pipelining of stream processing algorithms Public/Granted day:2015-12-08
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