Invention Application
- Patent Title: Reducing Retention Loss in Analog Floating Gate Memory
- Patent Title (中): 减少模拟浮动存储器中的保留损耗
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Application No.: US14546009Application Date: 2014-11-18
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Publication No.: US20150364480A1Publication Date: 2015-12-17
- Inventor: Allan T. Mitchell
- Applicant: Texas Instruments Incorporated
- Main IPC: H01L27/115
- IPC: H01L27/115 ; H01L21/326 ; H01L21/324

Abstract:
A conditioning process for integrated circuits including floating-gate devices, such as floating-gate capacitors or transistors in analog or other circuits in which the devices are to be programmed to a specific level. Following initial programming of the floating-gate devices to a specific programmed level, the integrated circuits are subjected to a conditioning bake, followed by re-trim back to the initial programmed level. That portion of the charge at the floating-gate device that was weakly held is removed by the conditioning bake, while the re-trim replaces that charge with more strongly held (i.e., higher activation energy) programmed charge.
Information query
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