Invention Application
US20150364491A1 SEMICONDUCTOR DEVICE INCLUDING SOI BUTTED JUNCTION TO REDUCE SHORT-CHANNEL PENALTY
有权
半导体器件,包括SOI引脚连接,以减少短路通道罚款
- Patent Title: SEMICONDUCTOR DEVICE INCLUDING SOI BUTTED JUNCTION TO REDUCE SHORT-CHANNEL PENALTY
- Patent Title (中): 半导体器件,包括SOI引脚连接,以减少短路通道罚款
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Application No.: US14832166Application Date: 2015-08-21
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Publication No.: US20150364491A1Publication Date: 2015-12-17
- Inventor: Viorel Ontalus , Robert R. Robison , Xin Wang
- Applicant: GLOBALFOUNDRIES Inc.
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/10 ; H01L29/78 ; H01L29/06

Abstract:
A semiconductor device comprises first and second gate stacks formed on a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a dielectric layer interposed between a bulk substrate layer and an active semiconductor layer. A first extension implant portion is disposed adjacent to the first gate stack and a second extension implant portion is disposed adjacent to the second gate stack. A halo implant extends continuously about the trench. A butting implant extends between the trench and the dielectric layer. An epitaxial layer is formed at the exposed region such that the butting implant is interposed between the epitaxial layer and the dielectric layer.
Public/Granted literature
- US09349749B2 Semiconductor device including SIU butted junction to reduce short-channel penalty Public/Granted day:2016-05-24
Information query
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