Invention Application
- Patent Title: METHOD FOR FABRICATING VERTICALLY STACKED NANOWIRES FOR SEMICONDUCTOR APPLICATIONS
- Patent Title (中): 用于制造半导体应用的垂直堆叠纳米线的方法
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Application No.: US14320590Application Date: 2014-06-30
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Publication No.: US20150372119A1Publication Date: 2015-12-24
- Inventor: Ying ZHANG , Hua CHUNG
- Applicant: Applied Materials, Inc.
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/06 ; H01L21/324 ; H01L21/265 ; H01L21/02

Abstract:
Embodiments of the present disclosure provide methods for forming nanowire structures with desired materials for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes performing an ion implantation process to dope dopants into a suspended nanowire structure on a substrate, the suspended nanowire includes multiple material layers having a spaced apart relationship repeatedly formed in the suspended nanowire structure, wherein the material layer predominantly comprises a first type of atoms formed therein, the dopants including a second type of atoms into the suspended nanowire structure, oxidating surfaces of the multiple material layers, and converting the first type of atoms in the material layer to the second type of atoms from the dopants doped therein.
Public/Granted literature
- US09419107B2 Method for fabricating vertically stacked nanowires for semiconductor applications Public/Granted day:2016-08-16
Information query
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