Invention Application
US20160005713A1 THREE DIMENSIONAL STACKED MULTI-CHIP STRUCTURE AND MANUFACTURING METHOD OF THE SAME 有权
三维堆叠多芯片结构及其制造方法

  • Patent Title: THREE DIMENSIONAL STACKED MULTI-CHIP STRUCTURE AND MANUFACTURING METHOD OF THE SAME
  • Patent Title (中): 三维堆叠多芯片结构及其制造方法
  • Application No.: US14324373
    Application Date: 2014-07-07
  • Publication No.: US20160005713A1
    Publication Date: 2016-01-07
  • Inventor: Shih-Hung Chen
  • Applicant: Macronix International Co., Ltd.
  • Main IPC: H01L25/065
  • IPC: H01L25/065 H01L25/00
THREE DIMENSIONAL STACKED MULTI-CHIP STRUCTURE AND MANUFACTURING METHOD OF THE SAME
Abstract:
A three dimensional stacked multi-chip structure including M chips, a first conductive pillar, and N second conductive pillars is provided. Each chip has a common connection area and a chip-enable area, and includes a substrate and a patterned circuit layer disposed on the substrate. The patterned circuit layer includes an active element, at least one common conductive structure in the common connection area, and N chip-enable conductive structures in the chip-enable area. The first conductive pillar connects the common conductive structure of the M chips. Each second conductive pillar connects one of the N chip-enable conductive structures of the M chips. The chip-conductive areas of the M chips have different conducting states. N is large than 1, M is large than 2, and M is smaller than or equal to 2N.
Information query
Patent Agency Ranking
0/0