A thin film transistor array panel includes: a substrate; a gate line and a common voltage line electrically separated from each other and elongated parallel with each other on the substrate; a gate insulating layer on the gate line and the common voltage line; a first passivation layer on the gate insulating layer; a common electrode on the first passivation layer; a second passivation layer on the common electrode; and a pixel electrode and a connection member on the second passivation layer and electrically separated from each other. The connection member is elongated in a horizontal direction parallel with the gate line and connects the common voltage line and the common electrode to each other.