Invention Application
- Patent Title: CHIP-STACKED SEMICONDUCTOR PACKAGE
- Patent Title (中): 芯片堆叠半导体封装
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Application No.: US14818682Application Date: 2015-08-05
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Publication No.: US20160056101A1Publication Date: 2016-02-25
- Inventor: Young-kun JEE , Tae-hong MIN , Sun-kyoung SEO
- Applicant: Young-kun JEE , Tae-hong MIN , Sun-kyoung SEO
- Priority: KR10-2014-0109958 20140822
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L25/065 ; H01L23/31

Abstract:
A chip-stacked semiconductor package including a first chip having a plurality of first real bump pads and a plurality of first dummy bump pads, a second chip on the first chip, the second chip including a plurality of real bumps and a plurality of bridge dummy bumps, the plurality of real bumps electrically connected to the plurality of first real bump pads, the plurality of bridge dummy bumps connected to the plurality of first dummy bump pads, and a sealing member sealing the first chip and the second chip may be provided.
Public/Granted literature
- US09543276B2 Chip-stacked semiconductor package Public/Granted day:2017-01-10
Information query
IPC分类: