Invention Application
- Patent Title: ELECTRICAL INTERCONNECT STRUCTURE FOR AN EMBEDDED SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THEREOF
- Patent Title (中): 嵌入式半导体器件封装的电气互连结构及其制造方法
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Application No.: US14464877Application Date: 2014-08-21
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Publication No.: US20160056136A1Publication Date: 2016-02-25
- Inventor: Paul Alan McConnelee , Arun Virupaksha Gowda
- Applicant: General Electric Company
- Main IPC: H01L25/16
- IPC: H01L25/16 ; H01L23/00 ; H01L21/768 ; H01L23/538 ; H01L23/522 ; H01L23/528 ; H01L23/532 ; H01L23/498 ; H01L25/00

Abstract:
An electronics package includes a first dielectric substrate having a first plurality of vias formed through a thickness thereof, a metalized contact layer coupled to a top surface of the first dielectric substrate, and a first die positioned within a first die opening formed through the thickness of the first dielectric substrate. Metalized interconnects are formed on a bottom surface of the first dielectric substrate and extend through the first plurality of vias to contact the metalized contact layer. A second dielectric substrate is coupled to the first dielectric substrate and has a second plurality of vias formed through a thickness thereof. Metalized interconnects extend through the second plurality of vias to contact the first plurality of metalized interconnects and contact pads of the first die. A first conductive element electrically couples the first die to the metalized contact layer.
Public/Granted literature
Information query
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