Invention Application
US20160056293A1 NON-PLANAR SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED FIN WITH TOP BLOCKING LAYER
有权
具有顶部阻挡层的自对准FIN的非平面半导体器件
- Patent Title: NON-PLANAR SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED FIN WITH TOP BLOCKING LAYER
- Patent Title (中): 具有顶部阻挡层的自对准FIN的非平面半导体器件
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Application No.: US14780218Application Date: 2013-06-26
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Publication No.: US20160056293A1Publication Date: 2016-02-25
- Inventor: JENG-YA D. YEH , CHIA-HONG JAN , WALID M. HAFEZ , JOODONG PARK
- Applicant: INTEL CORPORATION
- International Application: PCT/US13/47757 WO 20130626
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L29/423

Abstract:
Non-planar semiconductor devices having self-aligned fins with top blocking layers and methods of fabricating non-planar semiconductor devices having self-aligned fins with top blocking layers are described. For example, a semiconductor structure includes a semiconductor fin disposed above a semiconductor substrate and having a top surface. An isolation layer is disposed on either side of the semiconductor fin, and recessed below the top surface of the semiconductor fin to provide a protruding portion of the semiconductor fin. The protruding portion has sidewalls and the top surface. A gate blocking layer has a first portion disposed on at least a portion of the top surface of the semiconductor fin, and has a second portion disposed on at least a portion of the sidewalls of the semiconductor fin. The first portion of the gate blocking layer is continuous with, but thicker than, the second portion of the gate blocking layer. A gate stack is disposed on the first and second portions of the gate blocking layer.
Public/Granted literature
- US09780217B2 Non-planar semiconductor device having self-aligned fin with top blocking layer Public/Granted day:2017-10-03
Information query
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