发明申请
US20160064330A1 METHOD AND STRUCTURE TO REDUCE THE ELECTRIC FIELD IN SEMICONDUCTOR WIRING INTERCONNECTS 有权
减少半导体接线互连电场的方法和结构

METHOD AND STRUCTURE TO REDUCE THE ELECTRIC FIELD IN SEMICONDUCTOR WIRING INTERCONNECTS
摘要:
Embodiments of the present invention provide increased distance between vias and neighboring metal lines in a back end of line (BEOL) structure. A copper alloy seed layer is deposited in trenches that are formed in a dielectric layer. The trenches are then filled with copper. An anneal is then performed to create a self-forming barrier using a seed layer constituent, such as manganese, as the manganese is drawn to the dielectric layer during the anneal. The self-forming barrier is disposed on a shoulder region of the dielectric layer, increasing the effective distance between the via and its neighboring metal lines.
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