发明申请
- 专利标题: METHOD AND STRUCTURE TO REDUCE THE ELECTRIC FIELD IN SEMICONDUCTOR WIRING INTERCONNECTS
- 专利标题(中): 减少半导体接线互连电场的方法和结构
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申请号: US14883972申请日: 2015-10-15
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公开(公告)号: US20160064330A1公开(公告)日: 2016-03-03
- 发明人: Elbert Emin Huang , Takeshi Nogami , Raghuveer R. Patlolla , Christopher J. Penny , Theodorus Eduardus Standaert
- 申请人: International Business Machines Corporation
- 申请人地址: US NY Armonk
- 专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人: INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址: US NY Armonk
- 主分类号: H01L23/532
- IPC分类号: H01L23/532 ; H01L23/522
摘要:
Embodiments of the present invention provide increased distance between vias and neighboring metal lines in a back end of line (BEOL) structure. A copper alloy seed layer is deposited in trenches that are formed in a dielectric layer. The trenches are then filled with copper. An anneal is then performed to create a self-forming barrier using a seed layer constituent, such as manganese, as the manganese is drawn to the dielectric layer during the anneal. The self-forming barrier is disposed on a shoulder region of the dielectric layer, increasing the effective distance between the via and its neighboring metal lines.
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