发明申请
US20160109519A1 SYSTEM AND METHOD FOR ELIMINATING INDETERMINISM IN INTEGRATED CIRCUIT TESTING
审中-公开
用于消除集成电路测试中的不确定性的系统和方法
- 专利标题： SYSTEM AND METHOD FOR ELIMINATING INDETERMINISM IN INTEGRATED CIRCUIT TESTING
- 专利标题（中）： 用于消除集成电路测试中的不确定性的系统和方法
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申请号： US14516557申请日： 2014-10-16
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公开(公告)号： US20160109519A1公开(公告)日： 2016-04-21
- 发明人: Vishal Vadhavania , Akhil Jain , Sachin Jain , Arvind Garg
- 申请人： Vishal Vadhavania , Akhil Jain , Sachin Jain , Arvind Garg
- 主分类号： G01R31/317
- IPC分类号： G01R31/317 ; G01R31/3177
摘要：
Indeterministic launch of test transactions in a system-on-chip device having asynchronous paths may be avoided by gating test mode bus transactions at the functional (IP) module interface. The gated bus transactions are released using an external trigger in order to control loss of cycle accuracy caused by on-board synchronizers during functional testing. Conventional interfaces can be driven from automatic test equipment and controlled in order to account for PVT variations and achieve deterministic and stable behavior of the device while being tested.
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