The invention is a device for determining timing of a measured signal, the device comprising a plurality of flip-flop units (10), each having a clock signal input for receiving the measured signal (20) and a data input for receiving a secondary signal, and an evaluation module being adapted for evaluating outputs of the plurality flip-flop units (10), and the flip-flop units (10) are arranged on an FPGA architecture. The device according to the invention comprises an allocating module for allocating at least one path consisting of flip-flop units (10), wherein the measured signal (20) and the secondary signal are led to the flip-flop units (10) of the at least one path, and a calibration module being adapted for determining a time difference parameter of each flip-flop unit (10), the time difference parameter specifying for each flip-flop unit (10) a time difference between a period of time in which the measured signal (20) reaches the given flip-flop unit (10) from an input point of the measured signal and a period time in which the secondary signal reaches the given flip-flop unit (10) from an input point of the secondary signal, wherein the evaluation module is adapted for determining the timing of the measured signal from the output of the flip-flop units (10) located along the at least one path, on the basis of the time difference parameters. The invention is furthermore a method for determining timing of a measured signal.