Invention Application
US20160110113A1 Memory Compression Operable for Non-contiguous write/read Addresses
审中-公开
内存压缩可用于非连续写/读地址
- Patent Title: Memory Compression Operable for Non-contiguous write/read Addresses
- Patent Title (中): 内存压缩可用于非连续写/读地址
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Application No.: US14814617Application Date: 2015-07-31
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Publication No.: US20160110113A1Publication Date: 2016-04-21
- Inventor: Sundarrajan Rangachari , Desmond Pravin Martin Fernandes , Rakesh Channabasappa Yaraduyathinahalli
- Applicant: Texas Instruments Incorporated
- Priority: IN5194/CHE/2014 20141017
- Main IPC: G06F3/06
- IPC: G06F3/06

Abstract:
A digital data storage and retrieval system. The system has a first memory for storing a plurality of data quantities, and each data quantity, in the plurality of data quantities, consists of a first number of bits. The system also has a second memory for storing a plurality of compressed data quantities, and each compressed data quantity, in the plurality of compressed data quantities, consists of a second number of bits that is less than the first number of bits. The system also has circuitry for reading data quantities from the first memory and circuitry for writing compressed data quantities, corresponding to respective read data quantities, to non-sequential addresses in the second memory. The system also may include circuitry for reading compressed data quantities from the second memory, and circuitry for writing decompressed data quantities, corresponding to respective read compressed data quantities, to non-sequential addresses in the first memory.
Public/Granted literature
- US09793918B2 Memory compression operable for non-contiguous write/read addresses Public/Granted day:2017-10-17
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