Invention Application
- Patent Title: ELECTRONIC PACKAGE AND FABRICATION METHOD THEREOF
- Patent Title (中): 电子封装及其制造方法
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Application No.: US14862457Application Date: 2015-09-23
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Publication No.: US20160111359A1Publication Date: 2016-04-21
- Inventor: Yan-Heng Chen , Chun-Tang Lin , Mu-Hsuan Chan , Chieh-Yuan Chi
- Applicant: Siliconware Precision Industries Co., Ltd.
- Priority: TW103135624 20141015
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L21/48

Abstract:
A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.
Public/Granted literature
- US09899303B2 Electronic package and fabrication method thereof Public/Granted day:2018-02-20
Information query
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