Invention Application
- Patent Title: MULTI-CHANNEL GATE-ALL-AROUND FET
- Patent Title (中): 多通道门全接地FET
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Application No.: US14984688Application Date: 2015-12-30
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Publication No.: US20160111513A1Publication Date: 2016-04-21
- Inventor: Qing Liu , Ruilong Xie , Chun-chen Yeh , Xiuyu Cai
- Applicant: STMicroelectronics, Inc. , GlobalFoundries Inc. , International Business Machines Corporation
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L29/165 ; H01L29/06 ; H01L29/16 ; H01L29/786 ; H01L29/66

Abstract:
A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wraparound gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.
Public/Granted literature
- US09748352B2 Multi-channel gate-all-around FET Public/Granted day:2017-08-29
Information query
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