Invention Application
- Patent Title: INTEGRATED CIRCUIT TIMING VARIABILITY REDUCTION
- Patent Title (中): 集成电路时序可变性降低
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Application No.: US14525320Application Date: 2014-10-28
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Publication No.: US20160117433A1Publication Date: 2016-04-28
- Inventor: Eric A. Foreman , Chaitanya Kompalli , Sudeep Mandal , Sebastian T. Ventrone
- Applicant: GLOBALFOUNDRIES INC.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
As disclosed herein, a method, executed by a computer, for integrated circuit timing variability reduction includes loading a netlist that corresponds to a chip design, where the chip design includes one or more circuits and a plurality of post-fill features, traversing a portion of the netlist corresponding to a circuit, determining a post-fill environment for the circuit from a plurality of post-fill features, and modeling a timing variance for the circuit based on the post-fill environment. The method may also include changing one or more post-fill features to achieve a targeted delay. The method may include generating a report of circuit timing and timing variances. One or more circuits can be concurrently traversed. The timing variance can be modeled with the use of a scaling factor for a standard timing variance. A computer system and computer program product corresponding to the method are also disclosed herein.
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