A decoder 5 applies decode processing to N input data in parallel to generate K decode data. An S/P converter 6 outputs N input data applied in series to decoder 5 through first lines L1-L64 dividedly over several times. A P/S converter 7 receives through second lines R1-R60 the K decode data from decoder 5 dividedly over several times to output in series the K decoded data to an external source.