Invention Application
- Patent Title: Techniques for Interconnecting Stacked Dies Using Connection Sites
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Application No.: US15019867Application Date: 2016-02-09
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Publication No.: US20160172271A1Publication Date: 2016-06-16
- Inventor: Frederick A. Ware , Ely Tsern , Thomas Vogelsang
- Applicant: Rambus Inc.
- Main IPC: H01L23/48
- IPC: H01L23/48 ; G06F3/06
Abstract:
An integrated circuit die includes conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof. The integrated circuit also includes a core circuit located outside the contiguous region. The core circuit is coupled to at least one of the connection sites.
Public/Granted literature
- US09515008B2 Techniques for interconnecting stacked dies using connection sites Public/Granted day:2016-12-06
Information query
IPC分类:
