Invention Application
- Patent Title: SCAN TESTING SYSTEM, METHOD AND APPARATUS
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Application No.: US15078039Application Date: 2016-03-23
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Publication No.: US20160202319A1Publication Date: 2016-07-14
- Inventor: Lee D. Whetsel , Alan Hales
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Main IPC: G01R31/3177
- IPC: G01R31/3177

Abstract:
Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
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