Invention Application
- Patent Title: MULTI-LEVEL PAGING AND ADDRESS TRANSLATION IN A NETWORK ENVIRONMENT
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Application No.: US15077355Application Date: 2016-03-22
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Publication No.: US20160202918A1Publication Date: 2016-07-14
- Inventor: Sagar Borikar
- Applicant: CISCO TECHNOLOGY, INC.
- Applicant Address: US CA San Jose
- Assignee: CISCO TECHNOLOGY, INC.
- Current Assignee: CISCO TECHNOLOGY, INC.
- Current Assignee Address: US CA San Jose
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G06F12/10

Abstract:
An example method for facilitating multi-level paging and address translation in a network environment is provided and includes receiving a request for memory in a physical memory of a network element, associating the request with a first virtual address space, mapping a memory region located in the physical memory to a first window in the first virtual address space, the memory region being also mapped to a second window in a different, second virtual address space, remapping the first window in the first virtual address space to the second window in the second virtual address space, and responding to the request with addresses of the second window in the second virtual address space.
Public/Granted literature
- US09921970B2 Multi-level paging and address translation in a network environment Public/Granted day:2018-03-20
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