Invention Application
- Patent Title: VERIFICATION METHODS AND SYSTEMS FOR USE IN COMPUTER DIRECTED ASSEMBLY AND MANUFACTURE
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Application No.: US15084474Application Date: 2016-03-30
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Publication No.: US20160209836A1Publication Date: 2016-07-21
- Inventor: Balbir S. Rataul
- Applicant: Balbir S. Rataul
- Applicant Address: US CA MORGAN HILL
- Assignee: PARAMIT CORPORATION
- Current Assignee: PARAMIT CORPORATION
- Current Assignee Address: US CA MORGAN HILL
- Main IPC: G05B19/418
- IPC: G05B19/418

Abstract:
Verification methods, systems, and computer program products verify the completion of assembly instructions used in light-manufacturing. Using position guides in a user interface, an in-use component is aligned and ready for verification through a first set of images of the in-use component. A visual highlight area on the user interface overlaying the in-use component indicates where to perform the assembly instructions. To create a traceable record, a second set of images are stored in an assembly record database when the assembler points a wand where the in-use component has been assembled. Another verification approach includes pointing an image capture device over the in-use component and receiving a first voice command authorizing image acquisition. A second voice command confirms accuracy of the image and proper assembly. Storing first and second voice commands and images of the in-use component being assembled in an assembly record database creates another traceable record useful for verification.
Information query
IPC分类: