发明申请
US20160211849A1 NEGATIVE CAPACITANCE LOGIC DEVICE, CLOCK GENERATOR INCLUDING THE SAME AND METHOD OF OPERATING CLOCK GENERATOR
有权
负电容逻辑器件，包括其的时钟发生器和操作时钟发生器的方法
- 专利标题： NEGATIVE CAPACITANCE LOGIC DEVICE, CLOCK GENERATOR INCLUDING THE SAME AND METHOD OF OPERATING CLOCK GENERATOR
- 专利标题（中）： 负电容逻辑器件，包括其的时钟发生器和操作时钟发生器的方法
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申请号： US14614884申请日： 2015-02-05
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公开(公告)号： US20160211849A1公开(公告)日： 2016-07-21
- 发明人: Min Cheol Shin , Jae Hyun Lee , Doo Hyung Kang , Jun Beom Seo , Woo Jin Jeong
- 申请人： Min Cheol Shin , Jae Hyun Lee , Doo Hyung Kang , Jun Beom Seo , Woo Jin Jeong
- 申请人地址： KR Daejeon
- 专利权人： KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
- 当前专利权人： KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
- 当前专利权人地址： KR Daejeon
- 优先权： KR10-2015-0008700 20150119
- 主分类号： H03K19/16
- IPC分类号： H03K19/16 ; H03L7/26 ; H03B15/00 ; H03K19/0185
摘要：
A negative capacitance logic device includes a first field effect transistor (FET) and a second FET. The first FET is coupled between a power supply voltage and an output node, and the first FET includes a ferroelectric having a negative capacitance. The second FET is coupled between the output node and a ground voltage, and the second FET includes a ferroelectric having a negative capacitance. The negative capacitance logic differentiates an input voltage applied to an input node to provide an output voltage at the output node.