发明申请
- 专利标题: MODULATOR, PHASE LOCKED LOOP USING THE SAME, AND METHOD APPLIED THERETO
- 专利标题(中): 调制器,相位锁相环及其应用方法
-
申请号: US14943129申请日: 2015-11-17
-
公开(公告)号: US20160211967A1公开(公告)日: 2016-07-21
- 发明人: Yi-Chieh Huang , Ping-Ying Wang
- 申请人: MEDIATEK Inc.
- 主分类号: H04L7/02
- IPC分类号: H04L7/02 ; H03L7/093 ; H03L7/089
摘要:
A modulator for generating a control code in response to a frequency control word is provided. The modulator includes an adder, an accumulator, a next state generation unit, and a code generation unit. The adder generates a frequency error signal by calculating a difference between the frequency control word and the control code. The accumulator generates a phase error signal by accumulating the frequency error signal. The phase error signal includes an integer part and a fractional part. The integer part of the phase error signal is a current state signal. The next state generation unit generates a next state signal according to a characteristic probability distribution determined by the fractional part of the phase error signal. The code generation unit generates the control code in response to the current state signal and the next state signal.
公开/授权文献
信息查询