Multi-level conversion flip-flop circuits for multi-power domain integrated circuits (ICs) and related methods are disclosed. A flip-flop circuit latches a representation of a received input data signal in a lower voltage domain, in a latch circuit in a higher voltage domain without need for separate voltage level shifters. As a result, insertion loss/delay is minimized, thereby increasing performance. In certain aspects, the flip-flop circuits employ a gate-controlled, data control transistor to control activation of the latch circuit. By coupling the input data signal to a gate of the data control transistor, the input data signal in the lower voltage domain is not directly latched into the latch circuit. Instead, the data control transistor is configured to activate the latch circuit to latch a voltage in the higher voltage domain representing a logic value of the input data signal in the lower voltage domain in response to a clock signal.