发明申请
US20160336432A1 TRENCH VERTICAL JFET WITH IMPROVED THRESHOLD VOLTAGE CONTROL
审中-公开
具有改进的阈值电压控制的TRENCH VERTICAL JFET
- 专利标题: TRENCH VERTICAL JFET WITH IMPROVED THRESHOLD VOLTAGE CONTROL
- 专利标题(中): 具有改进的阈值电压控制的TRENCH VERTICAL JFET
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申请号: US15221641申请日: 2016-07-28
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公开(公告)号: US20160336432A1公开(公告)日: 2016-11-17
- 发明人: Anup Bhalla , Peter Alexandrov
- 申请人: United Silicon Carbide, Inc.
- 主分类号: H01L29/66
- IPC分类号: H01L29/66 ; H01L21/02 ; H01L21/306 ; H01L29/808
摘要:
Trench JFETs may be created by etching trenches into the topside of a substrate of a first doping type to form mesas. The substrate is made up of a backside drain layer, a middle drift layer, and topside source layer. The etching goes through the source layer and partly into the drift layer. Gate regions are formed on the sides and bottoms of the trenches using doping of a second type. Vertical channel regions are formed behind the vertical gate segments via angled implantation using a doping of the first kind, providing improved threshold voltage control. Optionally the substrate may include a lightly doped channel layer between the drift and source layers, such that the mesas include a lightly doped channel region that more strongly contrasts with the implanted vertical channel regions.
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