Invention Application
- Patent Title: BUILT-IN REDUNDANCY SCHEME FOR COMMUNICATION SYSTEM ON CHIP
- Patent Title (中): 内置通信系统冗余计划
-
Application No.: US15223326Application Date: 2016-07-29
-
Publication No.: US20160337046A1Publication Date: 2016-11-17
- Inventor: Radhakrishnan L. NAGARAJAN
- Applicant: INPHI CORPORATION
- Main IPC: H04B10/80
- IPC: H04B10/80 ; H04J14/02 ; H04L29/08 ; H04B10/54 ; H04B10/516 ; H04B10/69 ; H04B10/40 ; H04B10/556

Abstract:
In an example, the present invention includes an integrated system on chip device. The device has a redundancy block is configured to add at least redundancy bit as a function of one or more data bits associated with data for data error detection and correction data. In an example, the driver module is coupled to the signal processing blocking using a uni-directional multi-lane bus configured with N lanes, whereupon N is greater than M such that a difference between N and M represents a redundant lane or lanes. The device also has a mapping block configured to associate the M lanes to a plurality of selected laser devices for a silicon photonics device.
Public/Granted literature
- US09621280B2 Built-in redundancy scheme for communication system on chip Public/Granted day:2017-04-11
Information query