Invention Application
US20160361791A1 METHODS AND STRUCTURES FOR ACHIEVING TARGET RESISTANCE POST CMP USING IN-SITU RESISTANCE MEASUREMENTS 有权
使用现场电阻测量实现CMP后目标电阻的方法和结构

  • Patent Title: METHODS AND STRUCTURES FOR ACHIEVING TARGET RESISTANCE POST CMP USING IN-SITU RESISTANCE MEASUREMENTS
  • Patent Title (中): 使用现场电阻测量实现CMP后目标电阻的方法和结构
  • Application No.: US14737915
    Application Date: 2015-06-12
  • Publication No.: US20160361791A1
    Publication Date: 2016-12-15
  • Inventor: Laertis EconomikosElliott P. Rill
  • Applicant: GLOBALFOUNDRIES INC.
  • Main IPC: B24B37/005
  • IPC: B24B37/005 B24B37/20
METHODS AND STRUCTURES FOR ACHIEVING TARGET RESISTANCE POST CMP USING IN-SITU RESISTANCE MEASUREMENTS
Abstract:
Various particular embodiments include a method for controlling chemical mechanical polishing, including: polishing a semiconductor wafer in a chemical mechanical polishing (CMP) tool; measuring a resistance of a resistive pathway through the semiconductor wafer while the semiconductor wafer is undergoing polishing in the CMP tool; and terminating the polishing of the semiconductor wafer when the measured resistance reaches a target resistance.
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