Invention Application
- Patent Title: DUAL CHANNEL FINFET WITH RELAXED PFET REGION
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Application No.: US15252315Application Date: 2016-08-31
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Publication No.: US20160372493A1Publication Date: 2016-12-22
- Inventor: Xiuyu Cai , Qing Liu , Ruilong Xie , Chun-Chen Yeh
- Applicant: International Business Machines Corporation , GLOBALFOUNDRIES, Inc. , STMICROELECTRONICS, INC.
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/78 ; H01L27/092

Abstract:
Fabricating a semiconductor device includes providing a strained semiconductor material (SSM) layer disposed on a dielectric layer, forming a first plurality of fins on the SSOI structure, at least one fin of the first plurality of fins is in a nFET region and at least one fin is in a pFET region, etching portions of the dielectric layer under portions of the SSM layer of the at least one fin in the pFET region, filling areas cleared by the etching, forming a second plurality of fins from the at least one fin in the nFET region such that each fin comprises a portion of the SSM layer disposed on the dielectric layer, and forming a third plurality of fins from the at least one fin in the pFET region such that each fin comprises a portion of the SSM layer disposed on a flowable oxide.
Public/Granted literature
- US09559018B2 Dual channel finFET with relaxed pFET region Public/Granted day:2017-01-31
Information query
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