Invention Application
- Patent Title: METHOD FOR MANUFACTURING INSULATED GATE BIPOLAR TRANSISTOR
- Patent Title (中): 制造绝缘栅双极晶体管的方法
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Application No.: US14902432Application Date: 2014-08-25
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Publication No.: US20160380048A1Publication Date: 2016-12-29
- Inventor: Shengrong Zhong , Dongfei Zhou , Xiaoshe Deng , Genyi Wang
- Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.
- Priority: CN201310380034.3 20130827
- International Application: PCT/CN2014/085094 WO 20140825
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/739 ; H01L29/10 ; H01L21/761 ; H01L29/16 ; H01L29/20 ; H01L29/161 ; H01L29/04 ; H01L29/66 ; H01L29/40

Abstract:
A method for manufacturing an insulated gate bipolar transistor (100) comprises: providing a substrate (10), forming a field oxide layer (20) on a front surface of the substrate (10), and forming a terminal protection ring (23); performing photoetching and etching on the active region field oxide layer (20) by using an active region photomask, introducing N-type ions into the substrate (10) by using a photoresist as a mask film; depositing and forming a polysilicon gate (31) on the etched substrate (10) of the field oxide layer (20), and forming a protection layer on the polysilicon gate (31); performing junction pushing on an introduction region of the N-type ions, and then forming a carrier enhancement region (41); performing photoetching by using a P well photomask, introducing P-type ions into the carrier enhancement region (41), and performing junction pushing and then forming a P-body region; performing, by means of the polysilicon gate, self-alignment introduction of N-type ions into the P-body region, and performing junction pushing and then forming an N-type heavily doped region; forming sidewalls on two sides of the polysilicon gate, introducing P-type ions into the N-type heavily doped region, and performing junction pushing and then forming a P-type heavily doped region; and removing the protection layer, and then performing introduction and doping of the polysilicon gate. The method reduces a forward voltage drop disposing the carrier enhancement region.
Public/Granted literature
- US09590029B2 Method for manufacturing insulated gate bipolar transistor Public/Granted day:2017-03-07
Information query
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