Invention Application
- Patent Title: TEST STRUCTURE MACRO FOR MONITORING DIMENSIONS OF DEEP TRENCH ISOLATION REGIONS AND LOCAL TRENCH ISOLATION REGIONS
- Patent Title (中): 用于监测深层隔离区域和局部分离区域的尺寸的测试结构
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Application No.: US14789476Application Date: 2015-07-01
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Publication No.: US20170005014A1Publication Date: 2017-01-05
- Inventor: Tenko Yamashita , Chun-Chen Yeh , Hui Zang
- Applicant: International Business Machines Corporation , Globalfoundries, Inc.
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L29/06 ; H01L29/78 ; H01L21/768 ; H01L23/528 ; H01L23/522

Abstract:
Embodiments are directed to a method Embodiments are directed to a test structure of a fin-type field effect transistor (FinFET). The test structure includes a first conducting layer electrically coupled to a dummy gate of the FinFET, and a second conducting layer electrically coupled to a substrate of the FinFET. The test structure further includes a third conducting layer electrically coupled to the dummy gate of the FinFET, and a first region of the FinFET at least partially bound by the first conducting layer and the second conducting layer. The test structure further includes a second region of the FinFET at least partially bound by the second conducting layer and the third conducting layer, wherein the first region comprises a first dielectric having a first dimension, and wherein the second region comprises a second dielectric having a second dimension greater than the first dimension.
Public/Granted literature
Information query
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