Invention Application
- Patent Title: Method and Apparatus for Decimation in Frequency FFT Butterfly
- Patent Title (中): 频率FFT蝴蝶抽取的方法和装置
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Application No.: US15060475Application Date: 2016-03-03
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Publication No.: US20170011005A1Publication Date: 2017-01-12
- Inventor: Darrell Eugene Tinker
- Applicant: Tempo Semiconductor, Inc.
- Applicant Address: US TX Austin
- Assignee: Tempo Semiconductor, Inc.
- Current Assignee: Tempo Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: G06F17/14
- IPC: G06F17/14

Abstract:
A pipelined decimation in frequency FFT butterfly method, and an apparatus to perform this method comprising: a data memory with at least one read port and one write port; an add/subtract unit receiving data from the memory; a multiply/accumulate unit receiving data from the add/subtract unit; a source of coefficients, from logic gates or a coefficient memory, to supply FFT twiddle factors to the multiply/accumulate unit; a shifter receiving data from at least one of the add/subtract unit and the multiply/accumulate unit, the shifter supplying data to the write port of the data memory; wherein the apparatus performs these calculations in four cycles of the add/subtract unit and in four cycles of the multiply/accumulate unit, using complex arithmetic.
Public/Granted literature
- US09940303B2 Method and apparatus for decimation in frequency FFT butterfly Public/Granted day:2018-04-10
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