An array substrate according to an embodiment of the present disclosure may include a base substrate, a gate electrode, a gate insulating layer and an active layer arranged on the base substrate in a laminated way. The array substrate may further include a passivation layer arranged on the active layer, a source electrode, a drain electrode, a first electrode and a second electrode arranged on the passivation layer and on a same layer. A first via hole may be arranged in the passivation layer, and the first via hole may include two sloped lateral faces arranged opposite to each other. The first electrode may at least partially cover one lateral face of the first via hole, the second electrode may at least partially cover the other lateral face of the first via hole. The second electrode may be electrically connected to a common electrode lead. A second via hole may be further arranged in the passivation layer. The source electrode and the drain electrode may be connected to the active layer through the second via hole. And the first electrode may be electrically connected to the source electrode or the drain electrode.