Invention Application
US20170023957A1 BIAS TECHNIQUES AND CIRCUIT ARRANGEMENTS TO REDUCE LEAKAGE CURRENT IN A CIRCUIT
审中-公开
偏置技术和电路安排降低电路中的漏电流
- Patent Title: BIAS TECHNIQUES AND CIRCUIT ARRANGEMENTS TO REDUCE LEAKAGE CURRENT IN A CIRCUIT
- Patent Title (中): 偏置技术和电路安排降低电路中的漏电流
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Application No.: US15289504Application Date: 2016-10-10
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Publication No.: US20170023957A1Publication Date: 2017-01-26
- Inventor: Frederic Bossu , Ahmed Abdel Monem Youssef , Tsai-Pi Hung , Prasad Srinivasa Siva Gudem
- Applicant: QUALCOMM Incorporated
- Main IPC: G05F1/46
- IPC: G05F1/46 ; H02H9/04 ; H01L27/02
Abstract:
An apparatus includes an input/output (I/O) pin and an electrostatic discharge device. The electrostatic discharge device is coupled to the I/O pin and to a voltage regulator.
Information query
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