Invention Application
- Patent Title: STRUCTURES AND METHODS FOR SEMICONDUCTOR PACKAGING
- Patent Title (中): 用于半导体封装的结构和方法
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Application No.: US15222260Application Date: 2016-07-28
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Publication No.: US20170033058A1Publication Date: 2017-02-02
- Inventor: Quan Bang LI , ChingTi LIANG
- Applicant: Everspin Technologies, Inc.
- Applicant Address: US AZ Chandler
- Assignee: Everspin Technologies, Inc.
- Current Assignee: Everspin Technologies, Inc.
- Current Assignee Address: US AZ Chandler
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/495 ; H01L23/31
Abstract:
A semiconductor package including a lead frame having a die pad and a plurality of leads arranged along at least a portion of a periphery of the semiconductor package, a semiconductor die secured to the die pad, wherein at least a portion of the semiconductor die extends beyond a periphery of the die pad, and a molding material encapsulating the semiconductor die and at least a portion of the die pad.
Information query
IPC分类:
