Invention Application
- Patent Title: NEW FRACTIONAL PHASE LOCKED LOOP (PLL) ARCHITECTURE
- Patent Title (中): 新的相位锁相环（PLL）架构
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Application No.: US14820894Application Date: 2015-08-07
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Publication No.: US20170041005A1Publication Date: 2017-02-09
- Inventor: Bupesh Pandita , Hanan Cohen , Eskinder Hailu , Kenneth Luis Arcudia
- Applicant: QUALCOMM Incorporated
- Main IPC: H03K21/10
- IPC: H03K21/10
Abstract:
In one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider stages to a first one of the divider stages, and, for each of the divider stages, generating a respective local load signal when the modulus signal propagates out of the divider stage. The method also comprises, for each of the divider stages, inputting one or more respective control bits to the divider stage based on the respective local load signal, the one or more respective control bits setting a divider value of the divider stage.
Public/Granted literature
- US09577646B1 Fractional phase locked loop (PLL) architecture Public/Granted day:2017-02-21
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