Invention Application
US20170047248A1 FILLING CAVITIES IN AN INTEGRATED CIRCUIT AND RESULTING DEVICES
审中-公开
在集成电路和结果设备中填充CAVITIES
- Patent Title: FILLING CAVITIES IN AN INTEGRATED CIRCUIT AND RESULTING DEVICES
- Patent Title (中): 在集成电路和结果设备中填充CAVITIES
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Application No.: US15340181Application Date: 2016-11-01
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Publication No.: US20170047248A1Publication Date: 2017-02-16
- Inventor: Jonathan Lee RULLAN , Sunil Kumar SINGH
- Applicant: GLOBALFOUNDRIES Inc.
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/027 ; H01L23/532 ; H01L23/522 ; H01L23/528 ; H01L23/535

Abstract:
A methodology enabling filling of high aspect ratio cavities, with no voids or gaps, in an IC device and the resulting device are disclosed. Embodiments include providing active area and/or gate contacts in a first ILD; forming selective protective caps on upper surfaces of the contacts; forming a second ILD on upper surfaces of the protective caps and on an upper surface of the first ILD; forming a hard-mask stack on the second ILD; forming, in the second ILD and hard-mask stack, cavities exposing one or more protective caps; removing selective layers in the stack to decrease depths of the cavities; and filling the cavities with a metal layer, wherein the metal layer in one or more cavities connects to an upper surface of the one or more exposed protective caps.
Information query
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