Invention Application
US20170047275A1 REDUCING LEAD STRESS IN MICRO-ELECTRONIC PACKAGES 审中-公开
降低微电子封装中的引线应力

  • Patent Title: REDUCING LEAD STRESS IN MICRO-ELECTRONIC PACKAGES
  • Patent Title (中): 降低微电子封装中的引线应力
  • Application No.: US14823486
    Application Date: 2015-08-11
  • Publication No.: US20170047275A1
    Publication Date: 2017-02-16
  • Inventor: Wiwat Tanwongwan
  • Applicant: NXP B.V.
  • Main IPC: H01L23/495
  • IPC: H01L23/495 H01L21/56 H01L21/52
REDUCING LEAD STRESS IN MICRO-ELECTRONIC PACKAGES
Abstract:
Consistent with an example embodiment, there is a semiconductor device that comprises a lead frame assembly having a non-conductive material (NCM) sheet placed on a location of the lead frame assembly. A device die having a length, width, and thickness, is attached to the NCM sheet, the device die being attached to the NCM with an adhesive. The NCM sheet has a length and width greater than the length and width of the device die and the NCM sheet has a thickness less than the thickness of the device die. The NCM sheet mitigates wire bond lifting at device die bond pads by reducing bouncing of the wire bond leads owing to stress and movement of the lead frame assembly underneath the device die.
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