发明申请
US20170054447A1 BACKGROUND CALIBRATION OF INTERLEAVE TIMING ERRORS IN DIGITAL TO ANALOG CONVERTERS 有权
背景校正数字到模拟转换器的时序错误

  • 专利标题: BACKGROUND CALIBRATION OF INTERLEAVE TIMING ERRORS IN DIGITAL TO ANALOG CONVERTERS
  • 专利标题(中): 背景校正数字到模拟转换器的时序错误
  • 申请号: US15239067
    申请日: 2016-08-17
  • 公开(公告)号: US20170054447A1
    公开(公告)日: 2017-02-23
  • 发明人: Anthony Eugene ZORTEARussell ROMANO
  • 申请人: MULTIPHY LTD.
  • 申请人地址: IL Ness-Ziona
  • 专利权人: MULTIPHY LTD.
  • 当前专利权人: MULTIPHY LTD.
  • 当前专利权人地址: IL Ness-Ziona
  • 主分类号: H03M1/10
  • IPC分类号: H03M1/10 H03M1/66
BACKGROUND CALIBRATION OF INTERLEAVE TIMING ERRORS IN DIGITAL TO ANALOG CONVERTERS
摘要:
System and method for the calibration of interleave time errors in an n-level PAM Digital to Analog Converter (DAC), according to which a set of two samplers with adjustable sample time and threshold are introduced at the output of the DAC, which are separated in time. The set of samplers is swept through a n unit interval (UI) window and the n-UI window is classified to periods of transitions and non-transitions on an eye diagram. The relative timing of the lower rate clocks into an n:1 multiplexer is controlled using a control loop, to force equal eye width within the n-UI window and the interleaved timing errors are measured and corrected, until the uneven distribution is being reduced below a predetermined level.
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