A processor receives a command from a server computer to designate a plurality of addresses related to a plurality of logical storage areas, and write a plurality of write data to the logical storage areas. The processor receives the write data and writes it to storage areas different from storage areas in which a plurality of holding data are stored in a first memory. When the processor determines that the write data are written to the first memory, the processor transmits a success response to a host computer. When the write data satisfy a predetermined condition, the processor writes the write data in the first memory to a plurality of first device storage areas. When it is determined that at least a part of the data is not written to the first memory, the processor transmits a failure response to the host computer.