A display apparatus includes a display panel comprising a plurality of data lines and a plurality of gate lines crossing the plurality of data lines, a frequency detector configured to receive an input synchronization signal with an input frequency which is varying in a preset frequency range and to count clock cycles of an input frame in the input synchronization signal, and a synchronization signal generator configured to generate an output synchronization signal which has an insertion frame corresponding to a frame of maximum frequency within the preset frequency range and inset the insertion frame in a vertical blanking period of the input frame, based on the clock count.