Invention Application
US20170069579A1 SEMICONDUCTOR PACKAGES HAVING RESIDUAL STRESS LAYERS AND METHODS OF FABRICATING THE SAME 有权
具有残余应力层的半导体封装及其制造方法

  • Patent Title: SEMICONDUCTOR PACKAGES HAVING RESIDUAL STRESS LAYERS AND METHODS OF FABRICATING THE SAME
  • Patent Title (中): 具有残余应力层的半导体封装及其制造方法
  • Application No.: US15357154
    Application Date: 2016-11-21
  • Publication No.: US20170069579A1
    Publication Date: 2017-03-09
  • Inventor: YOUNGBAE KIM
  • Applicant: SAMSUNG ELECTRONICS CO., LTD.
  • Priority: KR10-2014-0084654 20140707
  • Main IPC: H01L23/00
  • IPC: H01L23/00 H01L25/10 H01L25/00
SEMICONDUCTOR PACKAGES HAVING RESIDUAL STRESS LAYERS AND METHODS OF FABRICATING THE SAME
Abstract:
A semiconductor package is provided. The semiconductor includes a lower package and an upper package stacked on the lower package. The lower package includes a package substrate, a semiconductor chip, a mold layer and a residential stress layer. The package substrate has upper and lower surfaces. The semiconductor chip is disposed on the upper surface of the package substrate. The mold layer encapsulates the semiconductor chip. The residual stress layer is disposed on the semiconductor chip. The residual stress layer includes a plastically deformed surface. The residual stress layer has a residual stress to counterbalance warpage of the lower package.
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