Invention Application
- Patent Title: COMPUTATION CIRCUIT, ENCODING CIRCUIT, AND DECODING CIRCUIT
- Patent Title (中): 计算电路，编码电路和解码电路
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Application No.: US15341249Application Date: 2016-11-02
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Publication No.: US20170077951A1Publication Date: 2017-03-16
- Inventor: Yoshinori TOMITA
- Applicant: FUJITSU LIMITED
- Applicant Address: JP Kawasaki-shi
- Assignee: FUJITSU LIMITED
- Current Assignee: FUJITSU LIMITED
- Current Assignee Address: JP Kawasaki-shi
- Main IPC: H03M13/07
- IPC: H03M13/07 ; H04L1/00
Abstract:
Memories retain data blocks on which exclusive logical OR computation is performed, and selection circuits receive a selection signal and select two or more data blocks for use in exclusive logical OR computation from among a plurality of data blocks read from the memories on the basis of the selection signal, and XOR circuits (exclusive logical OR computation circuits) perform exclusive logical OR computation based on the two or more data blocks selected by the selection circuits.
Information query
IPC分类:
