A digital signal processor is provided. The digital signal processor includes an execution circuit configured to receive a first data including first bits expressed in a signed magnitude method and a second data including second bits expressed in the signed magnitude method, and a control logic circuit configured to output a control signal that determines a type of operation on the first data and the second data based on a command signal, wherein the execution circuit is further configured to perform an operation on the first data and the second data according to a determined type of operation and generate a result of the operation.