- 专利标题: Instruction and Logic for Interrupt and Exception Handling
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申请号: US14865715申请日: 2015-09-25
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公开(公告)号: US20170090925A1公开(公告)日: 2017-03-30
- 发明人: Richard B. O'Connor , Beeman C. Strong , Michael W. Chynoweth , Rajshree A. Chabukswar
- 申请人: Richard B. O'Connor , Beeman C. Strong , Michael W. Chynoweth , Rajshree A. Chabukswar
- 主分类号: G06F9/30
- IPC分类号: G06F9/30 ; G06F9/38
摘要:
A processor includes a processor trace logical unit to produce branch execution records from execution of instructions. The processor further includes logic to determine that a condition has occurred on the processor during execution of the instructions. The condition is to include an asynchronous event or a return from a software handler for an asynchronous event. The processor further includes logic to determine whether event tracing is enabled for the processor. The processor also includes logic to generate a control flow event (CFE) packet. The CFE packet is to indicate a type of the condition. The processor further includes logic to generate an indicator of an instruction address that generated the condition.
公开/授权文献
- US10445204B2 Instruction and logic for interrupt and exception handling 公开/授权日:2019-10-15