Invention Application
- Patent Title: SCAN CHAIN LATCH DESIGN THAT IMPROVES TESTABILITY OF INTEGRATED CIRCUITS
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Application No.: US15138737Application Date: 2016-04-26
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Publication No.: US20170097389A1Publication Date: 2017-04-06
- Inventor: Dzmitry S. Maliuk , Franco Stellari , Alan J. Weger , Peilin Song
- Applicant: International Business Machines Corporation
- Main IPC: G01R31/317
- IPC: G01R31/317 ; G01R31/3177

Abstract:
A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency.
Public/Granted literature
- US09678152B2 Scan chain latch design that improves testability of integrated circuits Public/Granted day:2017-06-13
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